/*
Copyright (c) 2019 Alibaba Group Holding Limited

Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:

The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

*/
module is_top
    (
    //中断线
    input wire               apb0_dummy1_intr,
    input wire               apb0_dummy2_intr,
    input wire               apb0_dummy3_intr,
    input wire               apb0_dummy4_intr,
    input wire               apb0_dummy5_intr,
    input wire               apb0_dummy7_intr,
    input wire               apb0_dummy8_intr,
    input wire               apb0_dummy9_intr,
    input wire               apb1_dummy1_intr,
    input wire               apb1_dummy2_intr,
    input wire               apb1_dummy3_intr,
    input wire               apb1_dummy4_intr,
    input wire               apb1_dummy5_intr,
    input wire               apb1_dummy6_intr,
    input wire               apb1_dummy7_intr,
    input wire               apb1_dummy8_intr,
    input wire               lsbus_dummy0_intr,
    input wire               lsbus_dummy1_intr,
    input wire               lsbus_dummy2_intr,
    input wire               lsbus_dummy3_intr,
    input wire               gpio_wic_intr,
    input wire        [1 :0] tim0_wic_intr,
    input wire        [1 :0] tim1_wic_intr,
    input wire        [1 :0] tim2_wic_intr,
    input wire        [1 :0] tim3_wic_intr,
    input wire        [1 :0] tim4_wic_intr,
    input wire        [1 :0] tim5_wic_intr,
    input wire        [1 :0] tim6_wic_intr,
    input wire        [1 :0] tim7_wic_intr,
    input wire               usi0_wic_intr,
    input wire               usi1_wic_intr,
    input wire               usi2_wic_intr,
    input wire               wdt_wic_intr,
    input wire               pwm_wic_intr,
    input wire               rtc_wic_intr,
    //时钟复位线   
    input wire               ehs_ispmu_clk,
   
    input wire               pad_mcurst_b,
    input wire               wdt_ispmu_rst_b,
    input wire               padmux_cpu_jtg_tclk,
   
    //调试接口   
    input wire               cpu_padmux_jtg_tms_o,
    input wire               cpu_padmux_jtg_tms_oe,
    input wire               padmux_cpu_jtg_tms_i,
    //其它   

    //总线级联接口
    output wire       [31:0] hmain1_ree_bus_s10_haddr,
    output wire       [2 :0] hmain1_ree_bus_s10_hburst,
    output wire       [3 :0] hmain1_ree_bus_s10_hprot,
    output wire              hmain1_ree_bus_s10_hsel,
    output wire       [2 :0] hmain1_ree_bus_s10_hsize,
    output wire       [1 :0] hmain1_ree_bus_s10_htrans,
    output wire       [31:0] hmain1_ree_bus_s10_hwdata,
    output wire              hmain1_ree_bus_s10_hwrite,
    input wire        [31:0] ree_bus_hmain1_s10_hrdata,
    input wire               ree_bus_hmain1_s10_hready,
    input wire        [1 :0] ree_bus_hmain1_s10_hresp
    );  

wire                    bist0_mode;
wire                    scan_en;
wire                    scan_mode;
wire                    test_mode;
wire             [31:0] cpu_hmain1_m0_haddr;
reg              [31:0] cpu_hmain1_m0_offset_haddr;//经过偏移之后的地址
wire             [2 :0] cpu_hmain1_m0_hburst;
wire             [3 :0] cpu_hmain1_m0_hprot;
wire             [2 :0] cpu_hmain1_m0_hsize;
wire             [1 :0] cpu_hmain1_m0_htrans;
wire             [31:0] cpu_hmain1_m0_hwdata;
wire                    cpu_hmain1_m0_hwrite;
wire             [31:0] cpu_hmain1_m1_haddr;
reg              [31:0] cpu_hmain1_m1_offset_haddr;//经过偏移之后的地址
wire             [2 :0] cpu_hmain1_m1_hburst;
wire             [3 :0] cpu_hmain1_m1_hprot;
wire             [2 :0] cpu_hmain1_m1_hsize;
wire             [1 :0] cpu_hmain1_m1_htrans;
wire             [31:0] cpu_hmain1_m1_hwdata;
wire                    cpu_hmain1_m1_hwrite;
wire             [31:0] cpu_hmain1_m2_haddr;
reg              [31:0] cpu_hmain1_m2_offset_haddr;//经过偏移之后的地址
wire             [2 :0] cpu_hmain1_m2_hburst;
wire             [3 :0] cpu_hmain1_m2_hprot;
wire             [2 :0] cpu_hmain1_m2_hsize;
wire             [1 :0] cpu_hmain1_m2_htrans;
wire             [31:0] cpu_hmain1_m2_hwdata;
wire                    cpu_hmain1_m2_hwrite;
wire                    main_dummy4_intr;
wire             [31:0] hmain1_cpu_m0_hrdata;
wire                    hmain1_cpu_m0_hready;
wire             [1 :0] hmain1_cpu_m0_hresp;
wire             [31:0] hmain1_cpu_m1_hrdata;
wire                    hmain1_cpu_m1_hready;
wire             [1 :0] hmain1_cpu_m1_hresp;
wire             [31:0] hmain1_cpu_m2_hrdata;
wire                    hmain1_cpu_m2_hready;
wire             [1 :0] hmain1_cpu_m2_hresp;
wire                    main_dmemdummy0_intr;
wire                    main_dummy0_intr;
wire                    main_dummy1_intr;
wire                    main_dummy2_intr;
wire                    main_dummy3_intr;
wire                    main_imemdummy0_intr;
wire                    ispmu_wic_intr;
wire             [31:0] hmain1_ismc_s0_haddr;
wire             [3 :0] hmain1_ismc_s0_hprot;
wire                    hmain1_ismc_s0_hsel;
wire             [2 :0] hmain1_ismc_s0_hsize;
wire             [1 :0] hmain1_ismc_s0_htrans;
wire             [31:0] hmain1_ismc_s0_hwdata;
wire                    hmain1_ismc_s0_hwrite;
wire             [31:0] hmain1_smc_s2_haddr;
wire             [3 :0] hmain1_smc_s2_hprot;
wire                    hmain1_smc_s2_hsel;
wire             [2 :0] hmain1_smc_s2_hsize;
wire             [1 :0] hmain1_smc_s2_htrans;
wire             [31:0] hmain1_smc_s2_hwdata;
wire                    hmain1_smc_s2_hwrite;
wire             [31:0] hmain1_smc_s3_haddr;
wire             [3 :0] hmain1_smc_s3_hprot;
wire                    hmain1_smc_s3_hsel;
wire             [2 :0] hmain1_smc_s3_hsize;
wire             [1 :0] hmain1_smc_s3_htrans;
wire             [31:0] hmain1_smc_s3_hwdata;
wire                    hmain1_smc_s3_hwrite;
wire             [31:0] hmain1_smc_s4_haddr;
wire             [3 :0] hmain1_smc_s4_hprot;
wire                    hmain1_smc_s4_hsel;
wire             [2 :0] hmain1_smc_s4_hsize;
wire             [1 :0] hmain1_smc_s4_htrans;
wire             [31:0] hmain1_smc_s4_hwdata;
wire                    hmain1_smc_s4_hwrite;
wire             [31:0] ismc_hmain1_s0_hrdata;
wire                    ismc_hmain1_s0_hready;
wire             [1 :0] ismc_hmain1_s0_hresp;
wire             [31:0] smc_hmain1_s2_hrdata;
wire                    smc_hmain1_s2_hready;
wire             [1 :0] smc_hmain1_s2_hresp;
wire             [31:0] smc_hmain1_s3_hrdata;
wire                    smc_hmain1_s3_hready;
wire             [1 :0] smc_hmain1_s3_hresp;
wire             [31:0] smc_hmain1_s4_hrdata;
wire                    smc_hmain1_s4_hready;
wire             [1 :0] smc_hmain1_s4_hresp;

wire                    cpu_ispmu_dfs_ack;
wire                    cpu_ispmu_sleep_b;
wire                    ispmu_cpu_dfs_req;
wire                    dft_clk;
wire                    pad_core_clk;
wire                    pad_core_ctim_refclk;
wire                    pad_core_rst_b;

wire                    ispmu_smc_hclk;
wire                    ispmu_smc_hrst_b;
wire                    ispmu_dmemdummy0_hclk;
wire                    ispmu_dmemdummy0_hrst_b;
wire                    ispmu_dummy0_hclk;
wire                    ispmu_dummy0_hrst_b;
wire                    ispmu_dummy1_hclk;
wire                    ispmu_dummy1_hrst_b;
wire                    ispmu_dummy2_hclk;
wire                    ispmu_dummy2_hrst_b;
wire                    ispmu_dummy3_hclk;
wire                    ispmu_dummy3_hrst_b;
wire                    ispmu_dummy4_hclk;
wire                    ispmu_dummy4_hrst_b;
wire                    ispmu_hmain1_hclk;                                     //matrix bus clk
wire                    ispmu_hmain1_hrst_b;                                   //matrix bus rst
wire                    ispmu_imemdummy0_hclk;
wire                    ispmu_imemdummy0_hrst_b;
wire                    ispmu_mdummy0_hclk;
wire                    ispmu_mdummy0_hrst_b;
wire                    ispmu_mdummy1_hclk;
wire                    ispmu_mdummy1_hrst_b;
wire                    ispmu_mdummy2_hclk;
wire                    ispmu_mdummy2_hrst_b;
wire                    ispmu_mdummy3_hclk;
wire                    ispmu_mdummy3_hrst_b;




assign bist0_mode       = 1'b0;
assign scan_en          = 1'b0;
assign scan_mode        = 1'b0;
assign test_mode        = 1'b0;

//将core 的三根总线进行地址偏移，实现访问REE总线的目的
always @(*)    //优化组合逻辑
begin : CPU_HMAIN1_M0_OFFSET_HADDR                                             //指令总线
  // if ((cpu_hmain1_m0_haddr >= 32'h0000_0000)&&(cpu_hmain1_m0_haddr <= 32'h0000_FFFF))
  //   cpu_hmain1_m0_offset_haddr    = cpu_hmain1_m0_haddr + 32'hF000_0000;
  // else if ((cpu_hmain1_m0_haddr >= 32'h2000_0000)&&(cpu_hmain1_m0_haddr <= 32'h2000_FFFF))
  //   cpu_hmain1_m0_offset_haddr    = cpu_hmain1_m0_haddr + 32'hD002_0000;
  // else if ((cpu_hmain1_m0_haddr >= 32'h2001_0000)&&(cpu_hmain1_m0_haddr <= 32'h2001_FFFF))
  //   cpu_hmain1_m0_offset_haddr    = cpu_hmain1_m0_haddr + 32'hD002_0000;
  // else if ((cpu_hmain1_m0_haddr >= 32'h2002_0000)&&(cpu_hmain1_m0_haddr <= 32'h2002_FFFF))
  //   cpu_hmain1_m0_offset_haddr    = cpu_hmain1_m0_haddr + 32'hD002_0000;
  // else
    cpu_hmain1_m0_offset_haddr    = cpu_hmain1_m0_haddr;
end

always @(*) 
begin : CPU_HMAIN1_M1_OFFSET_HADDR                                             //cache总线
  // if ((cpu_hmain1_m1_haddr >= 32'h0000_0000)&&(cpu_hmain1_m1_haddr <= 32'h0000_FFFF))
  //   cpu_hmain1_m1_offset_haddr    = cpu_hmain1_m1_haddr + 32'hF000_0000;
  // else if ((cpu_hmain1_m1_haddr >= 32'h2000_0000)&&(cpu_hmain1_m1_haddr <= 32'h2000_FFFF))
  //   cpu_hmain1_m1_offset_haddr    = cpu_hmain1_m1_haddr + 32'hD002_0000;
  // else if ((cpu_hmain1_m1_haddr >= 32'h2001_0000)&&(cpu_hmain1_m1_haddr <= 32'h2001_FFFF))
  //   cpu_hmain1_m1_offset_haddr    = cpu_hmain1_m1_haddr + 32'hD002_0000;
  // else if ((cpu_hmain1_m1_haddr >= 32'h2002_0000)&&(cpu_hmain1_m1_haddr <= 32'h2002_FFFF))
  //   cpu_hmain1_m1_offset_haddr    = cpu_hmain1_m1_haddr + 32'hD002_0000;
  // else
    cpu_hmain1_m1_offset_haddr    = cpu_hmain1_m1_haddr;
end

always @(*) 
begin : CPU_HMAIN1_M2_OFFSET_HADDR                                             //系统总线
  // if ((cpu_hmain1_m2_haddr >= 32'h0000_0000)&&(cpu_hmain1_m2_haddr <= 32'h0000_FFFF))
  //   cpu_hmain1_m2_offset_haddr    = cpu_hmain1_m2_haddr + 32'hF000_0000;
  // else if ((cpu_hmain1_m2_haddr >= 32'h2000_0000)&&(cpu_hmain1_m2_haddr <= 32'h2000_FFFF))
  //   cpu_hmain1_m2_offset_haddr    = cpu_hmain1_m2_haddr + 32'hD002_0000;
  // else if ((cpu_hmain1_m2_haddr >= 32'h2001_0000)&&(cpu_hmain1_m2_haddr <= 32'h2001_FFFF))
  //   cpu_hmain1_m2_offset_haddr    = cpu_hmain1_m2_haddr + 32'hD002_0000;
  // else if ((cpu_hmain1_m2_haddr >= 32'h2002_0000)&&(cpu_hmain1_m2_haddr <= 32'h2002_FFFF))
  //   cpu_hmain1_m2_offset_haddr    = cpu_hmain1_m2_haddr + 32'hD002_0000;
  // else if ((cpu_hmain1_m2_haddr >= 32'hF002_0000)&&(cpu_hmain1_m2_haddr <= 32'hF004_FFFF))
  //   cpu_hmain1_m2_offset_haddr    = cpu_hmain1_m2_haddr - 32'hD002_0000;
  // else
    cpu_hmain1_m2_offset_haddr    = cpu_hmain1_m2_haddr;
end


is_tee_core_top
u_is_tee_core_top
    (
    .apb0_dummy1_intr                  (apb0_dummy1_intr                       ),
    .apb0_dummy2_intr                  (apb0_dummy2_intr                       ),
    .apb0_dummy3_intr                  (apb0_dummy3_intr                       ),
    .apb0_dummy4_intr                  (apb0_dummy4_intr                       ),
    .apb0_dummy5_intr                  (apb0_dummy5_intr                       ),
    .apb0_dummy7_intr                  (apb0_dummy7_intr                       ),
    .apb0_dummy8_intr                  (apb0_dummy8_intr                       ),
    .apb0_dummy9_intr                  (apb0_dummy9_intr                       ),
    .apb1_dummy1_intr                  (apb1_dummy1_intr                       ),
    .apb1_dummy2_intr                  (apb1_dummy2_intr                       ),
    .apb1_dummy3_intr                  (apb1_dummy3_intr                       ),
    .apb1_dummy4_intr                  (apb1_dummy4_intr                       ),
    .apb1_dummy5_intr                  (apb1_dummy5_intr                       ),
    .apb1_dummy6_intr                  (apb1_dummy6_intr                       ),
    .apb1_dummy7_intr                  (apb1_dummy7_intr                       ),
    .apb1_dummy8_intr                  (apb1_dummy8_intr                       ),
    .bist0_mode                        (bist0_mode                             ),
    .cpu_hmain1_m0_haddr               (cpu_hmain1_m0_haddr                    ),
    .cpu_hmain1_m0_hburst              (cpu_hmain1_m0_hburst                   ),
    .cpu_hmain1_m0_hprot               (cpu_hmain1_m0_hprot                    ),
    .cpu_hmain1_m0_hsize               (cpu_hmain1_m0_hsize                    ),
    .cpu_hmain1_m0_htrans              (cpu_hmain1_m0_htrans                   ),
    .cpu_hmain1_m0_hwdata              (cpu_hmain1_m0_hwdata                   ),
    .cpu_hmain1_m0_hwrite              (cpu_hmain1_m0_hwrite                   ),
    .cpu_hmain1_m1_haddr               (cpu_hmain1_m1_haddr                    ),
    .cpu_hmain1_m1_hburst              (cpu_hmain1_m1_hburst                   ),
    .cpu_hmain1_m1_hprot               (cpu_hmain1_m1_hprot                    ),
    .cpu_hmain1_m1_hsize               (cpu_hmain1_m1_hsize                    ),
    .cpu_hmain1_m1_htrans              (cpu_hmain1_m1_htrans                   ),
    .cpu_hmain1_m1_hwdata              (cpu_hmain1_m1_hwdata                   ),
    .cpu_hmain1_m1_hwrite              (cpu_hmain1_m1_hwrite                   ),
    .cpu_hmain1_m2_haddr               (cpu_hmain1_m2_haddr                    ),
    .cpu_hmain1_m2_hburst              (cpu_hmain1_m2_hburst                   ),
    .cpu_hmain1_m2_hprot               (cpu_hmain1_m2_hprot                    ),
    .cpu_hmain1_m2_hsize               (cpu_hmain1_m2_hsize                    ),
    .cpu_hmain1_m2_htrans              (cpu_hmain1_m2_htrans                   ),
    .cpu_hmain1_m2_hwdata              (cpu_hmain1_m2_hwdata                   ),
    .cpu_hmain1_m2_hwrite              (cpu_hmain1_m2_hwrite                   ),
    .cpu_padmux_jtg_tms_o              (cpu_padmux_jtg_tms_o                   ),
    .cpu_padmux_jtg_tms_oe             (cpu_padmux_jtg_tms_oe                  ),
    .cpu_ispmu_dfs_ack                 (cpu_ispmu_dfs_ack                      ),
    .cpu_ispmu_sleep_b                 (cpu_ispmu_sleep_b                      ),
    .dft_clk                           (dft_clk                                ),
    .dmac0_wic_intr                    (main_dummy4_intr                       ),
    .gpio_wic_intr                     (gpio_wic_intr                          ),
    .hmain1_cpu_m0_hrdata              (hmain1_cpu_m0_hrdata                   ),
    .hmain1_cpu_m0_hready              (hmain1_cpu_m0_hready                   ),
    .hmain1_cpu_m0_hresp               (hmain1_cpu_m0_hresp                    ),
    .hmain1_cpu_m1_hrdata              (hmain1_cpu_m1_hrdata                   ),
    .hmain1_cpu_m1_hready              (hmain1_cpu_m1_hready                   ),
    .hmain1_cpu_m1_hresp               (hmain1_cpu_m1_hresp                    ),
    .hmain1_cpu_m2_hrdata              (hmain1_cpu_m2_hrdata                   ),
    .hmain1_cpu_m2_hready              (hmain1_cpu_m2_hready                   ),
    .hmain1_cpu_m2_hresp               (hmain1_cpu_m2_hresp                    ),
    .lsbus_dummy0_intr                 (lsbus_dummy0_intr                      ),
    .lsbus_dummy1_intr                 (lsbus_dummy1_intr                      ),
    .lsbus_dummy2_intr                 (lsbus_dummy2_intr                      ),
    .lsbus_dummy3_intr                 (lsbus_dummy3_intr                      ),
    .main_dmemdummy0_intr              (main_dmemdummy0_intr                   ),
    .main_dummy0_intr                  (main_dummy0_intr                       ),
    .main_dummy1_intr                  (main_dummy1_intr                       ),
    .main_dummy2_intr                  (main_dummy2_intr                       ),
    .main_dummy3_intr                  (main_dummy3_intr                       ),
    .main_imemdummy0_intr              (main_imemdummy0_intr                   ),
    .pad_core_clk                      (pad_core_clk                           ),
    .pad_core_ctim_refclk              (pad_core_ctim_refclk                   ),
    .pad_core_rst_b                    (pad_core_rst_b                         ),
    .padmux_cpu_jtg_tclk               (padmux_cpu_jtg_tclk                    ),
    .padmux_cpu_jtg_tms_i              (padmux_cpu_jtg_tms_i                   ),
    .ispmu_cpu_dfs_req                 (ispmu_cpu_dfs_req                      ),
    .ispmu_wic_intr                    (ispmu_wic_intr                         ),
    .pwm_wic_intr                      (pwm_wic_intr                           ),
    .rtc_wic_intr                      (rtc_wic_intr                           ),
    .scan_en                           (scan_en                                ),
    .scan_mode                         (scan_mode                              ),
    .test_mode                         (test_mode                              ),
    .tim0_wic_intr                     (tim0_wic_intr                          ),
    .tim1_wic_intr                     (tim1_wic_intr                          ),
    .tim2_wic_intr                     (tim2_wic_intr                          ),
    .tim3_wic_intr                     (tim3_wic_intr                          ),
    .tim4_wic_intr                     (tim4_wic_intr                          ),
    .tim5_wic_intr                     (tim5_wic_intr                          ),
    .tim6_wic_intr                     (tim6_wic_intr                          ),
    .tim7_wic_intr                     (tim7_wic_intr                          ),
    .usi0_wic_intr                     (usi0_wic_intr                          ),
    .usi1_wic_intr                     (usi1_wic_intr                          ),
    .usi2_wic_intr                     (usi2_wic_intr                          ),
    .wdt_wic_intr                      (wdt_wic_intr                           )
);

is_bus_top
u_is_bus_top
    (
    .cpu_hmain1_m0_haddr               (cpu_hmain1_m0_offset_haddr             ),
    .cpu_hmain1_m0_hburst              (cpu_hmain1_m0_hburst                   ),
    .cpu_hmain1_m0_hprot               (cpu_hmain1_m0_hprot                    ),
    .cpu_hmain1_m0_hsize               (cpu_hmain1_m0_hsize                    ),
    .cpu_hmain1_m0_htrans              (cpu_hmain1_m0_htrans                   ),
    .cpu_hmain1_m0_hwdata              (cpu_hmain1_m0_hwdata                   ),
    .cpu_hmain1_m0_hwrite              (cpu_hmain1_m0_hwrite                   ),
    .cpu_hmain1_m1_haddr               (cpu_hmain1_m1_offset_haddr             ),
    .cpu_hmain1_m1_hburst              (cpu_hmain1_m1_hburst                   ),
    .cpu_hmain1_m1_hprot               (cpu_hmain1_m1_hprot                    ),
    .cpu_hmain1_m1_hsize               (cpu_hmain1_m1_hsize                    ),
    .cpu_hmain1_m1_htrans              (cpu_hmain1_m1_htrans                   ),
    .cpu_hmain1_m1_hwdata              (cpu_hmain1_m1_hwdata                   ),
    .cpu_hmain1_m1_hwrite              (cpu_hmain1_m1_hwrite                   ),
    .cpu_hmain1_m2_haddr               (cpu_hmain1_m2_offset_haddr             ),
    .cpu_hmain1_m2_hburst              (cpu_hmain1_m2_hburst                   ),
    .cpu_hmain1_m2_hprot               (cpu_hmain1_m2_hprot                    ),
    .cpu_hmain1_m2_hsize               (cpu_hmain1_m2_hsize                    ),
    .cpu_hmain1_m2_htrans              (cpu_hmain1_m2_htrans                   ),
    .cpu_hmain1_m2_hwdata              (cpu_hmain1_m2_hwdata                   ),
    .cpu_hmain1_m2_hwrite              (cpu_hmain1_m2_hwrite                   ),
    .hmain1_cpu_m0_hrdata              (hmain1_cpu_m0_hrdata                   ),
    .hmain1_cpu_m0_hready              (hmain1_cpu_m0_hready                   ),
    .hmain1_cpu_m0_hresp               (hmain1_cpu_m0_hresp                    ),
    .hmain1_cpu_m1_hrdata              (hmain1_cpu_m1_hrdata                   ),
    .hmain1_cpu_m1_hready              (hmain1_cpu_m1_hready                   ),
    .hmain1_cpu_m1_hresp               (hmain1_cpu_m1_hresp                    ),
    .hmain1_cpu_m2_hrdata              (hmain1_cpu_m2_hrdata                   ),
    .hmain1_cpu_m2_hready              (hmain1_cpu_m2_hready                   ),
    .hmain1_cpu_m2_hresp               (hmain1_cpu_m2_hresp                    ),
    .hmain1_ismc_s0_haddr              (hmain1_ismc_s0_haddr                   ),
    .hmain1_ismc_s0_hprot              (hmain1_ismc_s0_hprot                   ),
    .hmain1_ismc_s0_hsel               (hmain1_ismc_s0_hsel                    ),
    .hmain1_ismc_s0_hsize              (hmain1_ismc_s0_hsize                   ),
    .hmain1_ismc_s0_htrans             (hmain1_ismc_s0_htrans                  ),
    .hmain1_ismc_s0_hwdata             (hmain1_ismc_s0_hwdata                  ),
    .hmain1_ismc_s0_hwrite             (hmain1_ismc_s0_hwrite                  ),

/*
    .hmain1_ree_bus_s10_haddr          (               ),
    .hmain1_ree_bus_s10_hburst         (               ),
    .hmain1_ree_bus_s10_hprot          (               ),
    .hmain1_ree_bus_s10_hsize          (               ),
    .hmain1_ree_bus_s10_htrans         (               ),
    .hmain1_ree_bus_s10_hwdata         (               ),
    .hmain1_ree_bus_s10_hwrite         (               ),
*/

    .hmain1_ree_bus_s10_haddr          (hmain1_ree_bus_s10_haddr               ),
    .hmain1_ree_bus_s10_hburst         (hmain1_ree_bus_s10_hburst              ),
    .hmain1_ree_bus_s10_hprot          (hmain1_ree_bus_s10_hprot               ),
    .hmain1_ree_bus_s10_hsel           (hmain1_ree_bus_s10_hsel                ),
    .hmain1_ree_bus_s10_hsize          (hmain1_ree_bus_s10_hsize               ),
    .hmain1_ree_bus_s10_htrans         (hmain1_ree_bus_s10_htrans              ),
    .hmain1_ree_bus_s10_hwdata         (hmain1_ree_bus_s10_hwdata              ),
    .hmain1_ree_bus_s10_hwrite         (hmain1_ree_bus_s10_hwrite              ),

    .hmain1_smc_s2_haddr               (hmain1_smc_s2_haddr                    ),
    .hmain1_smc_s2_hprot               (hmain1_smc_s2_hprot                    ),
    .hmain1_smc_s2_hsel                (hmain1_smc_s2_hsel                     ),
    .hmain1_smc_s2_hsize               (hmain1_smc_s2_hsize                    ),
    .hmain1_smc_s2_htrans              (hmain1_smc_s2_htrans                   ),
    .hmain1_smc_s2_hwdata              (hmain1_smc_s2_hwdata                   ),
    .hmain1_smc_s2_hwrite              (hmain1_smc_s2_hwrite                   ),
    .hmain1_smc_s3_haddr               (hmain1_smc_s3_haddr                    ),
    .hmain1_smc_s3_hprot               (hmain1_smc_s3_hprot                    ),
    .hmain1_smc_s3_hsel                (hmain1_smc_s3_hsel                     ),
    .hmain1_smc_s3_hsize               (hmain1_smc_s3_hsize                    ),
    .hmain1_smc_s3_htrans              (hmain1_smc_s3_htrans                   ),
    .hmain1_smc_s3_hwdata              (hmain1_smc_s3_hwdata                   ),
    .hmain1_smc_s3_hwrite              (hmain1_smc_s3_hwrite                   ),
    .hmain1_smc_s4_haddr               (hmain1_smc_s4_haddr                    ),
    .hmain1_smc_s4_hprot               (hmain1_smc_s4_hprot                    ),
    .hmain1_smc_s4_hsel                (hmain1_smc_s4_hsel                     ),
    .hmain1_smc_s4_hsize               (hmain1_smc_s4_hsize                    ),
    .hmain1_smc_s4_htrans              (hmain1_smc_s4_htrans                   ),
    .hmain1_smc_s4_hwdata              (hmain1_smc_s4_hwdata                   ),
    .hmain1_smc_s4_hwrite              (hmain1_smc_s4_hwrite                   ),
    .ismc_hmain1_s0_hrdata             (ismc_hmain1_s0_hrdata                  ),
    .ismc_hmain1_s0_hready             (ismc_hmain1_s0_hready                  ),
    .ismc_hmain1_s0_hresp              (ismc_hmain1_s0_hresp                   ),
    .ree_bus_hmain1_s10_hrdata         (ree_bus_hmain1_s10_hrdata              ),
    .ree_bus_hmain1_s10_hready         (ree_bus_hmain1_s10_hready              ),
    .ree_bus_hmain1_s10_hresp          (ree_bus_hmain1_s10_hresp               ),
    .main_dmemdummy0_intr              (main_dmemdummy0_intr                   ),
    .main_dummy0_intr                  (main_dummy0_intr                       ),
    .main_dummy1_intr                  (main_dummy1_intr                       ),
    .main_dummy2_intr                  (main_dummy2_intr                       ),
    .main_dummy3_intr                  (main_dummy3_intr                       ),
    .main_dummy4_intr                  (main_dummy4_intr                       ),
    .main_imemdummy0_intr              (main_imemdummy0_intr                   ),
    .ispmu_dmemdummy0_hclk             (ispmu_dmemdummy0_hclk                  ),
    .ispmu_dmemdummy0_hrst_b           (ispmu_dmemdummy0_hrst_b                ),
    .ispmu_dummy0_hclk                 (ispmu_dummy0_hclk                      ),
    .ispmu_dummy0_hrst_b               (ispmu_dummy0_hrst_b                    ),
    .ispmu_dummy1_hclk                 (ispmu_dummy1_hclk                      ),
    .ispmu_dummy1_hrst_b               (ispmu_dummy1_hrst_b                    ),
    .ispmu_dummy2_hclk                 (ispmu_dummy2_hclk                      ),
    .ispmu_dummy2_hrst_b               (ispmu_dummy2_hrst_b                    ),
    .ispmu_dummy3_hclk                 (ispmu_dummy3_hclk                      ),
    .ispmu_dummy3_hrst_b               (ispmu_dummy3_hrst_b                    ),
    .ispmu_dummy4_hclk                 (ispmu_dummy4_hclk                      ),
    .ispmu_dummy4_hrst_b               (ispmu_dummy4_hrst_b                    ),
    .ispmu_hmain1_hclk                 (ispmu_hmain1_hclk                      ),
    .ispmu_hmain1_hrst_b               (ispmu_hmain1_hrst_b                    ),
    .ispmu_imemdummy0_hclk             (ispmu_imemdummy0_hclk                  ),
    .ispmu_imemdummy0_hrst_b           (ispmu_imemdummy0_hrst_b                ),
    .ispmu_mdummy0_hclk                (ispmu_mdummy0_hclk                     ),
    .ispmu_mdummy0_hrst_b              (ispmu_mdummy0_hrst_b                   ),
    .ispmu_mdummy1_hclk                (ispmu_mdummy1_hclk                     ),
    .ispmu_mdummy1_hrst_b              (ispmu_mdummy1_hrst_b                   ),
    .ispmu_mdummy2_hclk                (ispmu_mdummy2_hclk                     ),
    .ispmu_mdummy2_hrst_b              (ispmu_mdummy2_hrst_b                   ),
    .ispmu_mdummy3_hclk                (ispmu_mdummy3_hclk                     ),
    .ispmu_mdummy3_hrst_b              (ispmu_mdummy3_hrst_b                   ),
    .smc_hmain1_s2_hrdata              (smc_hmain1_s2_hrdata                   ),
    .smc_hmain1_s2_hready              (smc_hmain1_s2_hready                   ),
    .smc_hmain1_s2_hresp               (smc_hmain1_s2_hresp                    ),
    .smc_hmain1_s3_hrdata              (smc_hmain1_s3_hrdata                   ),
    .smc_hmain1_s3_hready              (smc_hmain1_s3_hready                   ),
    .smc_hmain1_s3_hresp               (smc_hmain1_s3_hresp                    ),
    .smc_hmain1_s4_hrdata              (smc_hmain1_s4_hrdata                   ),
    .smc_hmain1_s4_hready              (smc_hmain1_s4_hready                   ),
    .smc_hmain1_s4_hresp               (smc_hmain1_s4_hresp                    )
    );

is_xram_top
u_is_xram_top
    (
    .hmain1_ismc_s0_haddr              (hmain1_ismc_s0_haddr                   ),
    .hmain1_ismc_s0_hprot              (hmain1_ismc_s0_hprot                   ),
    .hmain1_ismc_s0_hsel               (hmain1_ismc_s0_hsel                    ),
    .hmain1_ismc_s0_hsize              (hmain1_ismc_s0_hsize                   ),
    .hmain1_ismc_s0_htrans             (hmain1_ismc_s0_htrans                  ),
    .hmain1_ismc_s0_hwdata             (hmain1_ismc_s0_hwdata                  ),
    .hmain1_ismc_s0_hwrite             (hmain1_ismc_s0_hwrite                  ),
    .hmain1_smc_s2_haddr               (hmain1_smc_s2_haddr                    ),
    .hmain1_smc_s2_hprot               (hmain1_smc_s2_hprot                    ),
    .hmain1_smc_s2_hsel                (hmain1_smc_s2_hsel                     ),
    .hmain1_smc_s2_hsize               (hmain1_smc_s2_hsize                    ),
    .hmain1_smc_s2_htrans              (hmain1_smc_s2_htrans                   ),
    .hmain1_smc_s2_hwdata              (hmain1_smc_s2_hwdata                   ),
    .hmain1_smc_s2_hwrite              (hmain1_smc_s2_hwrite                   ),
    .hmain1_smc_s3_haddr               (hmain1_smc_s3_haddr                    ),
    .hmain1_smc_s3_hprot               (hmain1_smc_s3_hprot                    ),
    .hmain1_smc_s3_hsel                (hmain1_smc_s3_hsel                     ),
    .hmain1_smc_s3_hsize               (hmain1_smc_s3_hsize                    ),
    .hmain1_smc_s3_htrans              (hmain1_smc_s3_htrans                   ),
    .hmain1_smc_s3_hwdata              (hmain1_smc_s3_hwdata                   ),
    .hmain1_smc_s3_hwrite              (hmain1_smc_s3_hwrite                   ),
    .hmain1_smc_s4_haddr               (hmain1_smc_s4_haddr                    ),
    .hmain1_smc_s4_hprot               (hmain1_smc_s4_hprot                    ),
    .hmain1_smc_s4_hsel                (hmain1_smc_s4_hsel                     ),
    .hmain1_smc_s4_hsize               (hmain1_smc_s4_hsize                    ),
    .hmain1_smc_s4_htrans              (hmain1_smc_s4_htrans                   ),
    .hmain1_smc_s4_hwdata              (hmain1_smc_s4_hwdata                   ),
    .hmain1_smc_s4_hwrite              (hmain1_smc_s4_hwrite                   ),
    .ismc_hmain1_s0_hrdata             (ismc_hmain1_s0_hrdata                  ),
    .ismc_hmain1_s0_hready             (ismc_hmain1_s0_hready                  ),
    .ismc_hmain1_s0_hresp              (ismc_hmain1_s0_hresp                   ),
    .pmu_smc_hclk                      (ispmu_smc_hclk                         ),
    .pmu_smc_hrst_b                    (ispmu_smc_hrst_b                       ),
    .smc_hmain1_s2_hrdata              (smc_hmain1_s2_hrdata                   ),
    .smc_hmain1_s2_hready              (smc_hmain1_s2_hready                   ),
    .smc_hmain1_s2_hresp               (smc_hmain1_s2_hresp                    ),
    .smc_hmain1_s3_hrdata              (smc_hmain1_s3_hrdata                   ),
    .smc_hmain1_s3_hready              (smc_hmain1_s3_hready                   ),
    .smc_hmain1_s3_hresp               (smc_hmain1_s3_hresp                    ),
    .smc_hmain1_s4_hrdata              (smc_hmain1_s4_hrdata                   ),
    .smc_hmain1_s4_hready              (smc_hmain1_s4_hready                   ),
    .smc_hmain1_s4_hresp               (smc_hmain1_s4_hresp                    )
);

is_pmu_top
u_is_pmu_top
    (
    .cpu_ispmu_dfs_ack                 (cpu_ispmu_dfs_ack                      ),
    .cpu_ispmu_sleep_b                 (cpu_ispmu_sleep_b                      ),
    .dft_clk                           (dft_clk                                ),
    .ehs_ispmu_clk                     (ehs_ispmu_clk                          ),
    .pad_core_clk                      (pad_core_clk                           ),
    .pad_core_ctim_refclk              (pad_core_ctim_refclk                   ),
    .pad_core_rst_b                    (pad_core_rst_b                         ),
    .pad_mcurst_b                      (pad_mcurst_b                           ),
    .ispmu_cpu_dfs_req                 (ispmu_cpu_dfs_req                      ),
    .ispmu_dummy4_hclk                 (ispmu_dummy4_hclk                      ),
    .ispmu_dummy4_hrst_b               (ispmu_dummy4_hrst_b                    ),
    .ispmu_mdummy3_hclk                (ispmu_mdummy3_hclk                     ),
    .ispmu_mdummy3_hrst_b              (ispmu_mdummy3_hrst_b                   ),
    .ispmu_dmemdummy0_hclk             (ispmu_dmemdummy0_hclk                  ),
    .ispmu_dmemdummy0_hrst_b           (ispmu_dmemdummy0_hrst_b                ),
    .ispmu_dummy0_hclk                 (ispmu_dummy0_hclk                      ),
    .ispmu_dummy0_hrst_b               (ispmu_dummy0_hrst_b                    ),
    .ispmu_dummy1_hclk                 (ispmu_dummy1_hclk                      ),
    .ispmu_dummy1_hrst_b               (ispmu_dummy1_hrst_b                    ),
    .ispmu_dummy2_hclk                 (ispmu_dummy2_hclk                      ),
    .ispmu_dummy2_hrst_b               (ispmu_dummy2_hrst_b                    ),
    .ispmu_dummy3_hclk                 (ispmu_dummy3_hclk                      ),
    .ispmu_dummy3_hrst_b               (ispmu_dummy3_hrst_b                    ),
    .ispmu_hmain0_hclk                 (ispmu_hmain1_hclk                      ),
    .ispmu_hmain0_hrst_b               (ispmu_hmain1_hrst_b                    ),
    .ispmu_imemdummy0_hclk             (ispmu_imemdummy0_hclk                  ),
    .ispmu_imemdummy0_hrst_b           (ispmu_imemdummy0_hrst_b                ),
    .ispmu_mdummy0_hclk                (ispmu_mdummy0_hclk                     ),
    .ispmu_mdummy0_hrst_b              (ispmu_mdummy0_hrst_b                   ),
    .ispmu_mdummy1_hclk                (ispmu_mdummy1_hclk                     ),
    .ispmu_mdummy1_hrst_b              (ispmu_mdummy1_hrst_b                   ),
    .ispmu_mdummy2_hclk                (ispmu_mdummy2_hclk                     ),
    .ispmu_mdummy2_hrst_b              (ispmu_mdummy2_hrst_b                   ),
    .ispmu_smc_hclk                    (ispmu_smc_hclk                         ),
    .ispmu_smc_hrst_b                  (ispmu_smc_hrst_b                       ),
    .ispmu_wic_intr                    (ispmu_wic_intr                         ),
    .wdt_ispmu_rst_b                   (wdt_ispmu_rst_b                        )
);

endmodule
